Strategies for Reducing Decoding Cycles in Stochastic LDPC Decoders

Published in TCASII, 2016

[Paper] [BibTex]


This brief presents three strategies, including initial- ization based on Look Up Table (LUT), postprocessing based on bit flipping and hard decision based on the posterior information, to reduce the number of decoding cycles (DCs) for stochastic low-density parity-check decoding. For the standard IEEE 802.3an code, simulation indicates a 73.6% reduction in the aver- age number of DCs with a satisfactory bit error rate. Moreover, hardware implementation shows that the area required for the proposed decoder is significantly reduced.