Strategies for Reducing Decoding Cycles in Stochastic LDPC Decoders

Abstract

This brief presents three strategies, including initialization based on Look Up Table (LUT), postprocessing based on bit flipping and hard decision based on the posterior information, to reduce the number of decoding cycles (DCs) for stochastic low-density parity-check decoding. For the standard IEEE 802.3an code, simulation indicates a 73.6% reduction in the average number of DCs with a satisfactory bit error rate. Moreover, hardware implementation shows that the area required for the proposed decoder is significantly reduced.

Publication
In IEEE Transactions on Circuits and Systems II-Express Briefs
Di Wu
Di Wu
PhD student

A Wisconsin Badger in Computer Architecture!

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