Low Latency

Convergence-Optimized Variable Node Structure for Stochastic LDPC Decoder

By using stochastic computation, a fully-parallel low-density parity-check (LDPC) decoder can be implemented using a lower wire complexity. In order to enhance the decoder performance, probability tracers, such as up/down counters, are added at each …

Strategies for Reducing Decoding Cycles in Stochastic LDPC Decoders

This brief presents three strategies, including initialization based on Look Up Table (LUT), postprocessing based on bit flipping and hard decision based on the posterior information, to reduce the number of decoding cycles (DCs) for stochastic …

Latency-Optimized Stochastic LDPC Decoder for High-Throughput Applications

Stochastic decoding can be applied to Low-Density Parity-Check codes in order to achieve high throughput with less area. However, most architectures suffer from large decoding latencies, due to the mechanism of stochastic computation. In this paper, …